The present invention relates to a charge transfer device.
A charge transfer device such as a bucket brigade device (BBD) or a charge coupled device (CCD) has been used as a delay line, a shift register or a memory. The memory is of a dynamic type using a shift register as memory elements. For the memory using charge transfer devices, the problem is how to obtain a high packing density.
Known driving systems for the charge transfer device are two-phase, three-phase and four-phase systems. These systems, however, need a plurality of storage cells for one bit. This disturbes it to make high the memory density. More particularly, two storage cells for one bit are necessary for the two- and four-phase driving systems; three storage cells for one bit are necessary for the three-phase driving system. Further, in any system, the signal charge transfer per bit is required a number of times (twice in the case of two-phase driving system and three times in the case of three-phase driving system). This results in a large transfer loss. To reduce the number of times of signal charge transfer and realize a memory with large capacity, the principle of an ME/B (multiplexed electrode per bit) structure is proposed in "1973 Tech. Dig. Papers, International Solid State Circuits Conference", Feb. 1973, pp 136 to 137, by D. R. Collins et al.
In the N-phase E/B structure are included a single empty storage cell and N-1 storage cells storing signal charges. The empty cell is shifted one cell each time a clock signal is applied thereto and the signal charges are shifted to the adjacent cells, respectively, after one cycle of clock signals. Accordingly, N-1 bits are formed by N signal charge storable regions. For this, the area per bit, compared with a charge transfer device by two-phase driving system, becomes (N/N-1).times.1/2. This means that, when the N is large, the memory density is approximately doubled.
In the ME/B structure, N shift registers of the E/B structure are connected in parallel and the signal charges are multiplexed at the input and output by N-phase clock pulses. In this structure, when each register has M stages, the shift register of (N-1).times.M bits is formed. Where the ME/B structure is realized with an existing driving system, the shift registers must be provided at the inputs with transfer gates, respectively, which are driven by separate clock pulses, in order to distribute successively input signal charges to the respective parallel shift registers. For this reason, in practice, 2N-phase clock pulses will be required. Furthermore, in the ME/B structure, shift registers must be so arranged that the registers are successively displaced by one phase at the input and output of the structure in the charge transfer direction. Thus, the structure has a problem in the layout and process when a large capacity memory is desired.